Erasable programmable read only memory (EPROM) cells commonly use FET devices with a floating gate structure on which charge can be stored The charge stored on the floating gate controls the threshold voltage, Vt, of the FET, and the logic state of the memory cell depends upon that Vt. Charge is added to or removed from the floating gate through the floating gate insulator using a capacitively coupled control gate stacked on the floating gate and separated therefrom by a control gate insulator.
The floating gate is typically charged by injecting hot carriers into the floating gate in the high electric field region adjacent the drain of the FET. When the floating gate is negatively charged, an n-channel FET is in a high Vt state. If sufficient charge is injected, the FET will be biased in a non-conducting state. Charge is removed from the floating gate by providing a voltage across the floating gate insulator sufficient to enable Fowler-Nordheim tunneling through that insulator from the floating gate. When the floating gate is discharged the FET is in a low Vt state. If sufficient charge is removed, the FET will be biased in a conducting state. The cell is read by detecting the magnitude of the current flowing through the FET, which varies with its Vt.
When operating the EPROM it is desirable to have the floating gate voltage track closely with the control gate voltage. To divide the voltage most advantageously, a large coupling capacitance between the floating gate and the control gate and a small coupling capacitance between the floating gate and everything else, such as the substrate and the source and drain regions, is therefore desirable. However, stacked floating and control gates need be of approximately the same size, making difficult the task of making control to floating gate capacitance significantly larger than floating gate to substrate or source/drain capacitance.
An alternate scheme, described in commonly assigned U.S. Pat. No. 5,465,231, to Ohsaki, describes an EEPROM cell formed of a pair of standard CMOS FETs having connected floating gates in which an n well serves as the control gate (or control electrode). While this scheme does not require additional process steps, it does require added surface area to accommodate the two FETs and the well.
Thus, a structure which decouples floating gate and control gate capacitances without requiring additional surface area is very desirable.